1 ps2015e 04/12/07 block diagram description: pericom semiconductor?s pi74fct373t and pi74fct 573t are 8-bit wide octal transparent latches designed with 3-state outputs and are intended for bus oriented applications. when latch enable (le) is high, the flip-flops appear transparent to the data. the data that meets the set-up time when le is low is latched. when oe is high, the bus output is in the high impedance state. pi74fct373t PI74FCT573T features: ? pi74fct373/573t are pin compatible with bipolar fast? series at a higher speed and lower power consumption ? ttl input and output levels ? low ground bounce outputs ? extremely low static power ? hysteresis on all inputs ? industrial operating temperature range: ?40c to +85c ? device models available upon request ? packaging: pi74fct373t (pb-free & green available) ? 20-pin tssop (l) ? 20-pin qsop (q) ? 20-pin soic (s) PI74FCT573T (pb-free & green available) ? 20-pin qsop (q) ? 20-pin soic (s) o d g oe le d 0 o 0 o d g d 1 o 1 o d g d 2 o 2 o d g d 3 o 3 o d g d 4 o 4 o d g d 5 o 5 o d g d 6 o 6 o d g d 7 o 7 octal transparent latches 06-0218
pi74fct373t PI74FCT573T octal transparent latches 2 ps2015e 04/12/07 inputs outputs d n le oe o n hhlh lhll xxhz truth table (1) notes: 1. h = high voltage level l = low voltage level x = don?t care z = high impedance pin name description oe output enable input (active low) le latch enable input (active high) d 0 -d 7 data inputs o 0 -o 7 3-state outputs o 0 -o 7 complementary 3-state outputs gnd ground v cc power pin description pi74fct373 pin configuration pi74fct573 pin configuration 20-pin q20 s20 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd vcc o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 le 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe o 0 d 0 d 1 o 1 o 2 d 2 d 3 o 3 gnd vcc o 7 d 7 d 6 o 6 o 5 d 5 d 4 o 4 le 06-0218
pi74fct373t PI74FCT573T octal transparent latches 3 ps2015e 04/12/07 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature ................................................................. ?65c to +150c ambient temperature with power applied ................................. -40c to +85c supply voltage to ground potential (inputs & vcc only) .......... ?0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ....... ?0.5v to +7.0v dc input voltage ......................................................................... ?0.5v to +7.0v dc output current ................................................................................... 120 ma power dissipation ......................................................................................... 0.5w note: stresses greater than those listed under maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (t a = 25c, f = 1 mhz) parameters (1) description test conditions typ max. units c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf notes: 1. this parameter is determined by device characterization but is not production tested. notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 5.0v 5%) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = ?15.0 ma 2.4 3.0 v v ol output low current v cc = min., v in = v ih or v il i ol = 64 ma 0.3 0.55 v v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current v cc = max. v in = v cc 1 a i il input low current v cc = max. v in = gnd ?1 a i ozh high impedance v cc = m ax .v out = 2.7v 1 a i ozl output current v out = 0.5v ?1 a v ik clamp diode voltage v cc = min., i in = ?18 ma ?0.7 ?1.2 v i off power down disable v cc = gnd, v out = 4.5v 100 a i os short circuit current v cc = max. (3) , v out = gnd ?60 ?120 ma v h input hysteresis 200 mv 06-0218
pi74fct373t PI74FCT573T octal transparent latches 4 ps2015e 04/12/07 power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = max. v in = gnd or v cc 0.1 500 a supply current i cc supply current per v cc = max., v in = 3.4v (3) 0.5 2.0 ma input @ ttl high i ccd supply current per v cc = max., v in = v cc 0.15 0.25 ma/ input per mhz (4) outputs open v in = gnd mhz oe = gnd le = v cc one bit toggling 50% duty cycle i c total power supply v cc = max., v in = v cc 1.5 3.0 (5) ma current (6) outputs open v in = gnd f i = 10 mh z 50% duty cycle oe = gnd v in = 3.4v 1.8 4.5 (5) le = v cc v in = gnd one bit toggling v cc = max., v in = v cc 3.0 6.0 (5) outputs open v in = gnd f i = 2.5 mh z 50% duty cycle oe = gnd v in = 3.4v 5.0 14.0 (5) le = v cc v in = gnd eight bits toggling notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice. 2. typical values are at vcc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + i cc d h n t + i ccd (f cp /2 + f i ni) i cc = quiescent current i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz. 06-0218
pi74fct373t PI74FCT573T octal transparent latches 5 ps2015e 04/12/07 pi74fct373t switching characteristics over operating range 373t 373at 373ct 373dt com. com. com. com. parameters description conditions min max min max min max min max unit t plh propagation delay (1) c l = 50 pf 1.5 8.0 1.5 5.2 1.5 4.2 1.5 3.8 ns t phl d n to o n r l = 500 t plh propagation delay (1) 2.0 13.0 2.0 8.5 2.0 5.5 1.5 4.9 ns t phl le to o n t pzh output enable time 1.5 12.0 1.5 6.5 1.5 5.5 1.5 5.5 ns t pzl oe to o n t phz output disable time (2) 1.5 7.5 1.5 5.5 1.5 5.0 1.5 5.0 ns t plz oe to o n t su setup time high or 2.0 2.0 2.0 2.0 ns low, d n to le t h hold time high or 1.5 1.5 1.5 1.5 ns low, d n to le t w le pulse width (2) 6.0 5.0 5.0 4.0 ns high notes: 1. minimum limits are guaranteed but not tested on propagation delays. 2. this parameter guaranteed but not production tested. PI74FCT573T switching characteristics over operating range 573t 573at 573ct 573dt com. com. com. com. parameters description conditions min max min max min max min max unit t plh propagation delay (1) c l = 50 pf 1.5 8.0 1.5 5.2 1.5 4.2 1.5 3.8 ns t phl d n to o n r l = 500 t plh propagation delay (1) 2.0 12.0 2.0 8.5 2.0 5.5 2.0 4.9 ns t phl le to o n t pzh output enable time 1.5 9.5 1.5 6.5 1.5 5.5 1.5 5.5 ns t pzl oe to o n t phz output disable time (2) 1.5 6.5 1.5 5.5 1.5 5.0 1.5 5.0 ns t plz oe to o n t su setup time high or 2.0 2.0 2.0 1.5 ns low, d n to le t h hold time high or 1.5 1.5 1.5 1.0 ns low, d n to le t w le pulse width (2) 6.0 5.0 5.0 3.0 ns high notes: 1. minimum limits are guaranteed but not tested on propagation delays. 2. this parameter guaranteed but not production tested. 06-0218
pi74fct373t PI74FCT573T octal transparent latches 6 ps2015e 04/12/07 packaging mechanical: 20-pin tssop (l) $ % 3 # 2 ) 0 4 ) / .
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pi74fct373t PI74FCT573T octal transparent latches 7 ps2015e 04/12/07 packaging mechanical: 20-pin qsop (q) 3 % ! 4 ) . ' 0 , ! . % " 3 # 8 8 8 8 8 8 $ % . / 4 % 3 $ ) - % . 3 ) / . 3 ) . - ) , , ) - % 4 % 2 3 x ? 2 % & $ e t a i l ! $ e t a i l ! - ) . ' u a g e 0 l a n e 2 % & ?
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pi74fct373t PI74FCT573T octal transparent latches 8 ps2015e 04/12/07 packaging mechanical: 20-pin soic (s) 3 % ! 4 ) . ' 0 , ! . % " 3 #
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pi74fct373t PI74FCT573T octal transparent latches 9 ps2015e 04/12/07 pi74fct373t ordering information ordering code package code speed grade package type pi74fct373tl l blank 20-pin tssop pi74fct373tle l blank pb-free & green, 20-pin tssop pi74fct373tq q blank 2 0-pin qsop pi74fct373tqe q blank pb-free & green, 20-pin qsop pi74fct373ts s blank 20-pin soic pi74fct373tse s blank pb-free & green, 20-pin soic pi74fct373atq q a 2 0-pin qsop pi74fct373atqe q a pb-free & green, 20-pin qsop pi74fct373ctl l c 20-pin tssop PI74FCT573T ordering information ordering code package code speed grade package type PI74FCT573Tq q blank pb-free & green, 20-pin qsop PI74FCT573Ts s blank 20-pin soic PI74FCT573Tse s blank pb-free & green, 20-pin soic pi74fct573ats s a 20-pin soic pi74fct573atse s a pb-free & green, 20-pin soic pi74fct573atq q a 20-pin qsop pi74fct573atqe q a pb-free & green, 20-pin qsop pi74fct573cts s c 20-pin soic pi74fct573ctse s c pb-free & green, 20-pin soic pi74fct573ctq q c 20-pin qsop pi74fct573ctqe q c pb-free & green, 20-pin qsop pi74fct573dtq q d 20-pin qsop pi74fct573dtqe q d pb-free & green, 20-pin qsop notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free & green ? adding an x suffix = tape/reel 06-0218
pi74fct373t PI74FCT573T octal transparent latches 10 ps2015e 04/12/07 pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com 06-0218
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